1. Field of the Invention
The present invention relates to a memory, and more particularly, it relates to a memory including memory cells holding data.
2. Description of the Background Art
A ferroelectric memory including memory cells holding data is known in general, as disclosed in Japanese Patent Laying-Open No. 2002-133857, for example.
In the ferroelectric memory including memory cells disclosed in the aforementioned Japanese Patent Laying-Open No. 2002-133857, a bit line connected to each memory cell and a capacitor storing charge are connected with each other through a charge transfer transistor controlling charge transfer from the bit line to the capacitor. In data reading, the memory determines the data held in the memory cell as “H” data or “L” data on the basis of a potential generated on a first electrode of the capacitor through change, corresponding to the data held in the memory cell, transferred to the capacitor through the bit line and the charge transfer transistor.
In the ferroelectric memory disclosed in the aforementioned Japanese Patent Laying-Open No. 2002-133857, however, the difference between the quantity of charge output to the bit line when the memory cell holds “H” data and that output to the bit line when the memory cell holds “L” data is disadvantageously reduced if the quantity of charge held in the memory cell is reduced due to downsizing of the ferroelectric memory or the like. In this case, the difference between the potential generated on the first electrode of the aforementioned capacitor when the memory reads “H” data from the memory cell and that generated on the first electrode of the capacitor when the memory reads “L” data is also reduced, and hence data determination accuracy is disadvantageously reduced when the memory determines the data on the basis of the potential generated on the first electrode of the capacitor